`timescale  1ns/1ns


module a0_test_top();

//******************************************************************************
//                              参数定义
//******************************************************************************
parameter             DW  = 1;
parameter integer     S = 7 ;                   // Set the serdes factor
parameter integer     D = 8 ;                   // Set the number of inputs and outputs
parameter integer     DS = (D*S)-1 ;            // Used for bus widths = serdes factor * number of inputs - 1

//******************************************************************************
//                              信号定义
//******************************************************************************
reg             resetb; 
reg             clk200M, pclk, L_oclk, R_oclk;
reg             L_clk100M_p, L_clk100M_n, R_clk100M_p, R_clk100M_n;


reg     [7:0]	vs;
reg     [7:0]	hs;
reg     [7:0]	de;
reg     [95:0]	data;

reg		[15:0]	f, h, l;

wire	[7:0]	vsin, hsin, dein;
wire	[95:0]	din;

//************************************************/
//      激励
//************************************************
initial begin
    resetb = 0;
    clk200M = 0;
    L_clk100M_p = 0;
    R_clk100M_p = 0;
    pclk = 0;
    L_oclk = 0;
    R_oclk = 0;
    
    #1_000;
    resetb = 1;
    
    #35_000;
    $stop();
end

always begin
    #2
    clk200M = 1;
    #3
    clk200M = 0;
    end

always begin
    #5
    L_clk100M_p = 1;
    #5
    L_clk100M_p = 0;
    end

always @( * )
	L_clk100M_n = ~L_clk100M_p;
	
always begin
    #5
    R_clk100M_p = 1;
    #5
    R_clk100M_p = 0;
    end

always @( * )
	R_clk100M_n = ~R_clk100M_p;
	
always begin
    #6
    pclk = 1;
    #7
    pclk = 0;
    end

always begin
    #6
    L_oclk = 1;
    #7
    L_oclk = 0;
    end

always begin
    #6
    R_oclk = 1;
    #7
    R_oclk = 0;
    end

always begin
    #7
    pclk = 1;
    #6
    pclk = 0;
    end
    

//时钟
reg [15:0]   H_DATA      = 12'd480;   //16'd240;
reg [15:0]   H_SYNC_S    = 12'd502;   //16'd251;//12'd255
reg [15:0]   H_SYNC_E    = 12'd513;   //16'd256;//12'd258
reg [15:0]   H_LENGTH    = 12'd550;   //16'd275;

reg [15:0]   V_DATA      = 12'd2160;  //16'd4320;
reg [15:0]   V_SYNC_S    = 12'd2245;  //16'd4494;//12'd4497
reg [15:0]   V_SYNC_E    = 12'd2247;  //16'd4498;//12'd4499
reg [15:0]   V_LENGTH    = 12'd2250;  //16'd4500;

initial begin
    vs = 0;
    hs = 0;
    de = 0;
    data = 0;
		
	#1_000;
	vs = 1;
	#1_000;
	vs = 0;
	
    #3_000;
    @(posedge pclk);
    repeat(10)@(posedge pclk);
    
    for (f = 0; f < 100; f = f + 1)begin
        for (h = 0; h < V_LENGTH; h = h + 1) begin
            for (l = 0; l < H_LENGTH; l = l + 1) begin
                @(posedge pclk);
                    begin
                        if (l < H_DATA && h< V_DATA)
                            de = 8'hff;
                        else 
                            de = 8'h00;
                        
                        if ( h>= V_SYNC_S && h< V_SYNC_E )
                            vs = 8'hff;
                        else 
                            vs = 8'h00;
                        
                        if (l>= H_SYNC_S && l < H_SYNC_E) 
                            hs =  8'hff;
                        else 
                            hs =  8'h00;

                    	if (de[0] == 0)
                    		data = 0;
                    	else if (h == 3)
                    		data = 0;
						else if (h == 1)
                    		data = {4{8'h02, 8'h01, 8'h00}};
						else if (h == 2)
                    		data = {4{8'hFF, 8'hFE, 8'hFD}};
						else
                    		data = {8'h00, 8'h00, l[5:0], 2'b11, 8'h00, 8'h00, l[5:0], 2'b10, 8'h00, 8'h00, l[5:0], 2'b01, 8'h00, 8'h00, l[5:0], 2'b00 };
						                            
                    end
            end
        end
    end
    
end

assign	vsin = vs;
assign	hsin = hs;
assign	dein = de;
assign	din = data;

//给缓冲区赋值，用于测试插入无效数据
defparam	h_compress.TEST_ENLARGE	= 1;

reg		[15:0]	addr;

initial begin
    for (addr = 0; addr < 2048; addr = addr + 1)
		h_compress.sram_dp.mem[addr] = {11'h000, addr[10:0], 2'b11, 11'h000, addr[10:0], 2'b10, 11'h000, addr[10:0], 2'b01, 11'h000, addr[10:0], 2'b00};
end

reg		[12:0]	unit_size, comp_size, out_size;
reg		[28:0]	adjust_coe;
integer			temp;

//测试参数
initial begin
	unit_size = 47;
	comp_size = 33;
	out_size = 47;
	temp = unit_size * 65536;
	temp = temp / comp_size;
	adjust_coe = temp;
	end

h_compress h_compress
(
	.resetb(resetb),
	.sclk(pclk),

	.adjust_coe(adjust_coe),
	.unit_size(unit_size),
	.comp_size(comp_size),
	.out_size(out_size),

	.dein(dein),
	.din(din),
    
	.deout(),
	.dout(),
    
	.tout()
);

/************************************************/
//      调试信号
/************************************************/
assign  tout = 0;


endmodule


